1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic products. More particularly, the present invention relates to etch stop layers and etch stop methods for fabricating microelectronic products.
2. Description of the Related Art
Common in the art of semiconductor product fabrication is the use of complementary metal oxide semiconductor (CMOS) devices formed within and upon semiconductor substrates. CMOS devices, such as CMOS field effect transistor (FET) devices, are generally of interest within semiconductor products insofar as CMOS devices may often be readily fabricated to provide low power consumption circuits within semiconductor products.
While CMOS devices are thus clearly desirable and often essential in the art of semiconductor product fabrication, CMOS devices are nonetheless not entirely without problems.
In that regard, it is often difficult in the art of semiconductor product fabrication to fabricate CMOS devices with enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of semiconductor product fabrication for fabricating CMOS devices with desirable properties.
Included among the methods, but not limiting among the methods are methods disclosed within: (1) Wang et al., in U.S. Pat. No. 6,187,655 (a pre-amorphizing implant (PAI) method for forming CMOS devices with reduced resist protect oxide (RPO) layer damage and reduced junction leakage); and (2) Chou et al., in U.S. Pat. No. 6,348,389 (an RPO etch method with enhanced endpoint detection for use when fabricating CMOS devices).
Desirable in the art of semiconductor product fabrication are additional methods for fabricating CMOS devices with enhanced performance.
It is towards the foregoing object that the present invention is directed.